The present invention relates to a semiconductor device and a method for producing the same, and more particularly to a highly miniaturized semiconductor device and a method for producing such highly miniaturized semiconductor device.
FIG. 4A shows one example of a conventional semiconductor device such as a transistor. On a silicon semiconductor substrate 1, there are provided a dielectric device isolation layer 2 by a LOCOS method, a gate insulating layer 3, aside wall insulation layer 4, low impurity concentration diffusion layer regions 5a and high impurity concentration (N+ type) diffusion layer regions 5b serving as a source and a drain, and a gate electrode 6 formed of polycrystalline silicon containing impurities. FIG. 4A shows a fabrication stage in which an oxide film which had been formed over the gate electrode 6 and the diffusion layer regions 5b has been removed therefrom.
Recent technical trends are pointing toward high-speed semiconductor devices having extremely small dimensions. Therefore, an extremely minute pattern size, and particularly fine dimensions for the gate electrode 6 and the high impurity concentration diffusion layer regions 5b are required. However, miniaturization tends to increase lead resistance, thereby leading to degradation of transistor efficiency.
In order to obviate this drawback, it has been proposed to form a refractory metal silicide layer upon the gate electrode 6 and the high impurity concentration diffusion layer regions 5b. Refractory metal silicide has been considered because it has a sheet resistivity of from 2 to 10.OMEGA. per square, which resistivity is considerably smaller than that of the polycrystalline silicon material of the gate electrode 6 and the high impurity concentration diffusion layer 5b, so that increases in the resistance of the leads attendant to miniaturization of the device can be avoided or at least minimized.
One proposal made by coworkers of the inventors with respect to use of the silicide layer in a semiconductor device is shown in FIGS. 4B through 4D.
Firstly, in FIG. 4B, a titanium layer 7 having a thickness of from 300 to 1500 .ANG. is formed by a known sputtering method over the entire surfaces of the dielectric isolation 2, the gate insulating layer 3, the side wall insulation region 4, the low impurity concentration diffusion layer regions 5a, the high impurity concentration diffusion layer regions 5b and the gate electrode 6 made of polycrystalline silicon containing impurities, those elements being formed on the silicon substrate 1. Then, a heat treatment is conducted at a temperature ranging from 500.degree. C. to 900.degree. C. in a nitrogen atmosphere.
As a result of the heat treatment, the titanium layer 7 in contact with the silicon, i.e., with the gate electrode 6 and the high impurity concentration diffusion layer regions 5b, is converted into titanium silicide 8 because of the reaction between the titanium and the silicon, whereas the remaining portions of titanium layer 7 in contact with the dielectric isolation 2, the side wall dielectric isolation 4 and the gate insulator 3 is converted into a titanium nitride, TiN, because of the reaction between the titanium and the ambient nitrogen gas.
Thereafter, the titanium nitride layer is subjected to etching by a mixture of ammonia and hydrogen peroxide, so that only regions of titanium silicide 8 remain on a top surface of the interim device, as best shown in FIG. 4C. Thus, titanium silicide 8 is present only on gate electrode 6 and diffusion layer regions 5b.
FIG. 4D shows an electrical connection achieved on one N.sup.+ type diffusion layer region 5b in a multi-layered lead structure in which a first lead portion consists of the diffusion layer region 5b and a region of titanium silicide 8. An intervening, or intermediate, insulation layer 9 is provided over regions of titanium silicide 8 and dielectric isolation 2, and a second, upper, lead portion 11 of polycrystalline silicon is deposited on insulation layer 9. For electrically connecting the first and the second lead portions together, a contact hole 10 reaching the region of titanium silicide 8 is formed in insulation layer 9 at a position above the diffusion layer region 5b by a conventional dry etching method which involves masking with a photo-resist. Accordingly, the polycrystalline silicon of the second lead layer 11 can enter into the contact hole to be brought into contact with the first lead portion. Thus, the upper polycrystalline silicon layer 11 can be connected to the diffusion layer region 5b via the titanium silicide layer 8. In other words, the first and the second lead portions can be electrically connected together.
FIG. 4E is a cross-sectional view of a semiconductor device according to another proposal. The cross-sectional plane of FIG. 4E is perpendicular to that of FIGS. 4A through 4D for description of an electrical connection on the N-type polycrystalline silicon. In this proposal, a first lead portion of a multi-layered lead consists of the gate electrode 6 formed of polycrystalline silicon with added impurities and a layer of titanium silicide 8 deposited thereon. Similar to FIG. 4D, the intermediate insulation layer 9 is formed over the silicide layer 8 and the dielectric isolation 2, and a second lead portion 11 made of polycrystalline silicon is formed over the intermediate insulating layer 9. To be more specific, a contact hole 10 reaching the titanium silicide layer 8 is formed in intermediate insulation layer 9 at a position above gate electrode 6 by a conventional dry etching method. Through the contact hole 10, the gate electrode 6 and the second lead portion 11 are electrically connected together via the titanium silicide layer 8. That is, the material of the second lead portion 11 enters into the contact hole 10, so that the polycrystalline silicon of the upper lead portion 11 is brought into contact with the polycrystalline silicon of the electrode 6 through the titanium silicide layer 8.
In the above-mentioned dry etching process to form hole 10 at an intended portion of insulation layer 9, photoresist is removed for providing the contact hole 10 by the application of an oxygen plasma or sulfuric acid, and a part of the titanium silicide 8 is exposed upon formation of the contact hole lo. Thus, the surface is exposed to an oxygen atmosphere. Further, upon completion of the dry etching process, a part of the titanium silicide layer 8 at a position within the contact hole 10 is exposed to an oxygen atmosphere. Consequently, an unwanted oxide film may be formed at the exposed surface of the titanium silicide 8.
A report has been released relating to ohmic contact between titanium silicide and polycrystalline silicon in a provisional contribution No. 2 P58829a-SB-20 released at No. 37, Applied Physical Society, held in 1990, and entitled "PolySi direct contact characteristic onto TiSi.sub.2 membrane". According to the report, if no titanium silicide exists, an inferior product rate is almost zero. On the other hand, provided that the titanium silicide layer is provided, the inferior product rate may be lowered if a pre-treatment is effected so as to remove an oxide film over the titanium silicide by BHF (buffered hydrofluoric acid, which is a mixed acid of hydrofluoric acid and ammonium fluoride). Here, if structures shown in FIGS. 4D and 4E are premised, and if such BHF treatment is conducted for etching the oxidized surface of the titanium silicide layer 8, excessive etching occurs. That is, the hydrofluoric acid etches not only the titanium silicide 8 within contact hole 10 but also a portion radially outside the boundary of contact hole 10 as shown in FIG. 5. As a result, an unwanted undercut portion 10a is provided by the excessive etching. This undercut may lead to generation of voids in a resultant semiconductor device, to thereby degrade reliability of the device.
The contribution reported that improvement can be made in the ohmic contact characteristic, if the polycrystalline silicon is deposited on the titanium silicide layer without the BHF treatment and ion beam mixing is carried out at a boundary surface thereof by arsenic ion implantation or silicon ion implantation. However, according to the report, inferior production rate was still high with respect to the N+ diffusion layer even by the implantation of arsenic or silicon ions. Generally, in ion beam mixing, the implanted ions impart energy to atoms in a substrate, and the atoms run out of lattice points, so that atoms of the substrate are mixed with atoms of an upper thin layer. Here, the high ratio of the inferior production is considered to be due to the fact that the oxide film of the titanium silicide, the film being positioned at the boundary between the titanium silicide layer and the polycrystalline silicon layer, prevents the atoms from passing therethrough. In this respect, an improvement was made on the inferior production rate with respect to N-type polycrystalline silicon in comparison With the N.sup.+ diffusion layer. The reason therefor resides in that the atoms may easily pass through the oxide film during the ion mixing process in case of implantation on the N-type polycrystalline silicon layer rather than N.sup.+ diffusion layer. In an attempt to further improve the atom mixing effect, if the ion implantation is carried out after the removal of the oxide film by the BHF treatment, then excessive etching by the hydrofluoric acid may disadvantageously occur, as described above. As a result, substantial improvements would not be attainable.